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S3C72H8/p72h8 product overview 1- 1 1 product overview overview the S3C72H8 single-chip cmos microcontroller has been designed for very high performance using samsung's state-of-the-art 4 -bit product developme nt approach, sam47 (samsung arrangeable microcontrollers). its main features are an up-to-13-digit lcd direct drive capability, 2-channel comparator inputs and outputs, and versatile 8-counter/ timers and 16-bit frequency counter. the S3C72H8 gives you an excellent design solution for a variety of lcd-related applications, specially thermostat control application. up to 21 pins of the available 64-pin qfp packages can be dedicated to i/o. and six vectored interrupts provide fast response to internal and external events. in addition, the S3C72H8's advanced cmos technology provides for low power consumption and a wide oper - ating voltage range.
product overview S3C72H8/p72h8 1- 2 features architecture ? sam47 4-bit cpu core memory ? data memory: 512 4 bit s ? program memory: 8196 8 bit s (including lcd display ram) memory-mapped i/o structure ? data memory bank 15 interrupts ? three internal vectored interrupts ? three external vectored interrupts ? two quasi-interrupts 8-bit timer/counter (t0) ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider 16-bit frequency counter (fc) ? a 16-bit binary up-counter ? external event counter ? gate function control watch-dog timer and basic timer ? 8-bit counter + 3-bit counter ? overflow signal of 8-bit counter makes a basic timer interrupt. and control the oscillation warm- up time ? overflow signal of 3-bit counter makes a system reset watch timer ? real-time an d interval time measurement ? four frequency outputs to buzzer sound ? clock source generation for lcd lcd controller/driver ? 26 segment and 4 common terminals ? maximum 13-digit lcd direct drive capability ? display modes: static, 1/2, 1/3, 1/4 duty ? voltage regulator and booster (1/3 bias: 1, 2, or 3v, 1/2 bias: 1.5, 3v) analog comparator ? 2 ch comparator (each cnp, cnn, cnout pins) bit sequential carrier ? support 16-bit serial data transfer in arbitrary format i/o p ort s ? 21 pins for standard i/o ? 26 pins for lcd segment output ? 4 pins for lcd common output ? two input pins for external interrupts oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64 main, and by 4 for sub clock ) power down mode ? idle mode (only cpu clock stops) ? stop mode (main or sub-system oscillation stops) voltage level detector ? v dd level detection circuit (2.2, 2.4, 3, or 4.0v) ? external pin level detect mode operating voltage range ? 1.8v to 5.5v at 3 mhz ? 2.0v to 5.5v at 4.19 mhz package type ? 64 -pin qfp
S3C72H8/p72h8 product overview 1- 3 block diagram program status word stack pointer arithmetic and logic unit internal interrupts reset instruction register 512 x 4-bit data memory p0.0/extref p0.1/sdat p0.2/sclk com0-com3 fcl i/o port 4,5 i/o port 0 i/o port 2 i/o port 3 i/o port 6 p2.0/int0 p2.1/int1 p2.2/tcl0 p2.3/fcl p3.0/tclo0 p3.1/btco p3.2/clo p3.3/buz p4.0/c0p p4.1/c0n p4.2/c0out p4.3/c1out p5.0/c1p p5.1/c1n p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 interrupt control block program counter clock otp block instruction decoder 8 k byte program memory voltage level detector two analog comparator extref cnp cn out cnn int0, int1 v pp / test x out x in xt out xt in sclk sdat voltage booster watch timer basic timer 16-bit freq counter 8-bit timer lcd driver/ controller watchdog timer c0 out c1 out tcl0 tclo0 seg0-seg25 ca, cb v lc0 -v lc2 figure 1 -1 . S3C72H8 simplified block diagram
product overview S3C72H8/p72h8 1- 4 pin assignments ca cb v lc0 v lc1 v lc2 p0.0/extref sdat /p0.1 sclk /p0.2 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset / reset p2.0/int0 p2.1/int1 p2.2/tcl0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 p2.3/fcl p3.0/tclo0 p3.1/btco p3.2/clo p3.3/buz p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 p4.0/c0p p4.1/c0n p4.2/c0out p4.3pc1out S3C72H8 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 p5.1/c1n p5.0/c1p 51 50 43 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 figure 1 -2 . S3C72H8 pin assignment diagram
S3C72H8/p72h8 product overview 1- 5 pin descriptions table 1 - 1. S3C72H8 pin descriptions pin name pin type description number (64-qfp) share pin circuit type p0.0 p0.1 p0.2 i/o 3-bit i/o port. 1-bit and 4-bit read/write and test is possible. port 0 is software configurable as input or output. 3-bit pull-up resistors are software assignable. 6 7 8 extref ? ? d-1 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable. 17 18 19 20 int0 int1 tcl0 fcl d-1 p3.0 p3.1 p3.2 p3.3 i/o same as port 2. ports 2 and 3 can be addressed by 1, 4, and 8-bit read/write and test instruction. 21 22 23 24 tclo0 btco clo buz d-1 p4.0-p4.3 p5.0-p5.1 i/o 4/2-bit i/o ports. n-channel open-drain or push-pull output. 1, 4, and 8-bit read/write and test is possible. ports 4 and 5 can be paired to support 8-bit data transfer. pull-up resistors are assignable to port unit by software control. 29-32 33-34 c0p/ c0n/ c0out/ c1out c1p/ c1n e-1 p6.0-p6.3 i/o 4-bit i/o ports. port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 25-28 ks0-ks3 d-1 btco i/o basic timer clock output 22 p3.1 d-1 clo i/o cpu clock output 23 p3.2 d-1 buz i/o 2, 4, 8 or 16 khz frequency output for buzzer sound with 4.19mhz main-system clock or 32.768 khz sub-system clock. 24 p3.3 d-1 x out , x in ? crystal, ceramic, or rc oscillator signal for main- system clock. (for external clock input, use x in and input x in ?s reverse phase to x out ) 11, 12 ? ? xt out , xt in ? crystal oscillator signal for sub-system clock. (for external clock input, use xt in and input xt in ?s reverse phase to xt out ) 14, 15 ? ? int0, int1 i/o external interrupts. the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 17, 18 p2.0, p2.1 d-1
product overview S3C72H8/p72h8 1- 6 table 1 - 1. S3C72H8 pin descriptio ns (continued) pin name pin type description number (64-qfp) share pin circuit type ks0-ks3 i/o quasi-interrupt input with falling edge detection 25-28 p6.0-p6.3 d-1 extref i/o external reference input 6 p0.0 d-1 tcl0 i/o external clock input for timer/counter 0 19 p2.2 d-1 fcl i/o external clock input for frequency counter 20 p2.3 d-1 tclo0 i/o timer/counter 0 clock output 21 p3.0 d-1 com0-com3 o lcd common signal output 61-64 ? h-16 seg0-seg25 o lcd segment output 35-60 ? h-16 ca, cb ? voltage booster capacitor pins 1, 2 ? ? v lc0 -v lc2 ? voltage booster output pins (v lc0 is the regulated output, v lc1 is the 2* v lc0 output, v lc2 is the 3* v lc0 output) 3-5 ? ? c0p, c0n, c0out i/o comparator 0 non-inverting input, inverting input and output. c0out can be configured as c-mos push-pull or n-ch open drain output 29-31 p4.0-p4.2 ? c1p, c1n, c1out i/o i comparator 1 non-inverting input, inverting input and output. c1out can be configured as c-mos push-pull or n-ch open drain output 32-34 p4.3-p5.1 ? reset ? reset signal for chip initialization 16 ? b v dd ? main power supply 9 ? ? v ss ? ground 10 ? ? test ? test signal input (must be connected to v ss ) 13 v pp ? sdat i/o serial data for otp programming 7 p0.1 sclk i/o serial clock for otp programming 8 p0.2 v pp ? power supply pin for eprom cell writing 13 test note: pull-up resistors for ports 0, 2, 3, and 6 are automatically disabled if they are configured to output mo de. but pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode.
S3C72H8/p72h8 product overview 1- 7 pin circuit diagrams p-channel n-channel in v dd figure 1 -3. pin circuit type a v dd out output disable data p-channel n-channel figure 1 -5. pin circuit type c in v dd figure 1 -4. pin circuit type b (reset) i/o circuit type c pull-up resistor p-cannel output disable data v dd resistor enable input disable figure 1 -6. pin circuit type d-1 (p0, p2, p3, p6)
product overview S3C72H8/p72h8 1- 8 v dd pull-up enable v dd in/out pne output disable data input disable to data bus to comparator figure 1 -7 . pin circuit type e-1 (p4, p5) out v lc2 v lc1 seg/com data v lc0 figure 1 -8 . pin circuit type h-16 (com/seg)
S3C72H8/p72h8 electrical data 16- 1 16 electrical data overview in this section, information on S3C72H8 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abso lute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data retention supply volt age in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data S3C72H8/p72h8 16- 2 table 16- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i n ? ? 0.3 to v dd + 0.3 output voltage v o all i/o ports ? 0.3 to v dd + 0.3 output current high i oh one i/o p in active ? 7 ma all i/o ports active ? 40 output current low i ol one i/o pin active + 15 ma total pin circuit + 60 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 table 16- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units operation v oltage v dd f osc = 6 mhz (cpu clock = 1.25 mhz) 2.7 ? 5.5 v f osc = 4.19 mhz (instruction clock = 1.04 mhz) 2.0 5.5 f osc = 3 mhz (cpu clock = 0.75 mhz) 1.8 5.5 input high v i h1 p0, p2, p3, p4, p5 and p6 0.8 v dd ? v dd v oltage v i h 2 reset 0.85 v dd v dd v i h 3 x in v dd -0.1 v dd input l ow v il1 p0, p2, p3, p4, p5 and p6 ? 0.2 v dd v oltage v il2 reset 0.3 v dd v il3 x in 0.1 output high v oltage v oh1 v dd = 5.0 v i oh = ? 1 ma all output pins v dd ? 1 .0 ? ? v i oh = ? 100 m a v dd ? 0.5 output l ow v oltage v ol1 v dd = 5.0 v, i ol = 2 ma all output pins except v ol2 ? 0.4 0.5 v ol2 v dd = 5.0 v , i ol = 1 5 ma ports 2,3, and 4 0.4 1.0
S3C72H8/p72h8 electrical data 16- 3 table 16- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input h igh leakage c urrent (note) i lih1 v in = v dd all input pins ? ? 3 a input low leakage c urrent (note) i lil1 v in = v dd ; all input pins except reset ? ? ? 3 output h igh l eakage c urrent (note) i loh v out = v dd all i/o pins and output pins ? ? 3 output l ow l eakage c urrent (note) i lol v o ut = 0 v all i/o pins and output pins ? ? ? 3 pull-up r esistor s r l1 v in = 0 v , v dd = 5 v t a = 25 c , ports 0-6 25 47 100 k w v dd = 3 v 50 90 150 r l2 v in = 0 v; v dd = 5 .0 v 150 250 350 t a = 25 c , reset oscillator feed back resistors r osc1 v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0v 400 700 1200 r osc2 v dd = 5.0 v, t a = 25 c xt in = v dd , xt out = 0v 1000 1500 3000 |v lc1 -comi| voltage drop (i = 0-3) v dc -15 ua per common pin ? ? 120 mv |v lc1 -segi| voltage drop (i = 0-25) v ds -15 ua per segment pin ? ? 120 note : except x in , x out , xt in , xt out
electrical data S3C72H8/p72h8 16- 4 table 16- 2. d.c. electrical characteristics (con tinu ed) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (note) i dd1 main operation mode: v dd = 5 v 10%, 6-mhz crystal ? 3.5 8 ma v dd = 5 v 10%, 4.19 mhz 2.5 5.5 v dd = 3 v 10%, 6-mhz crystal 1.6 4 v dd = 3 v 10%, 4.19 mhz 1.2 3 i dd2 main idle mode: v dd = 5 v 10%, 6-mhz crystal ? 1.8 3.5 v dd = 5 v 10%, 4.19 mhz 1.4 3.0 v dd = 3 v 10%, 6-mhz crystal 0.6 1.2 v dd = 3 v 10%, 4.19 mhz 0.5 1.1 i dd3 sub operation mode: v dd = 3 v , 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 15 30 ua i dd4 sub idle mode; v dd = 3 .0, 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 6 15 i dd5 stop mode; main & sub osc stop, v dd =5 v 10% except i vd, i vld, icomp and external load. scmod = 0100b xt in = 0v- ? 0.3 3 ua stop & sub osc stop, v dd = 3 v , except i vd, i vld, lcomp and external load. 0.1 1 note: supply current does not include current drawn through internal pull-up resistors or external output current loads. i lcd is lcd controller/driver operating current, i vb is voltage booster current, icomp is comparator current and i vld is voltage level detector current. table 16-3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr 1.0 - 5.5 v data retention supply current i dddr v dddr = 1.0 v stop mode; main & sub osc stop. except i vb , i vld , i lcd and external load. - - 1 ua
S3C72H8/p72h8 electrical data 16- 5 table 16-4 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator c1 c2 x in x out oscillation frequency (1) ? 0.4 ? 6 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 2.0 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator r x in x out frequency (1) v dd = 5 v r = 25 k, v dd = 5 v r = 50 k , v dd = 3 v 0.4 ? 2.0 1.0 2.5 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
electrical data S3C72H8/p72h8 16- 6 table 16-5 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in xt out c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 us notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs. table 16-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s t ime (1 ) v dd = 1.8 v to 5 .5 v 1.33 ? 64 tcl0 , fcl input f ti0 , f ti0 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz f requency v dd = 1.8 v to 5 .5v 1 tcl0 , fcl i nput t tih0, t til0 v dd = 2.7 v to 5.5 v 150 ? ? ns h igh, low w idth t fch , t fcl v dd = 1.8 v to 5 .5 v 250 interrupt input t inth, int0 (2) ? ? s high, low width t intl int1, int2 (ks0-ks3) 10 reset input low width t rsl input 10 ? ? s notes 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock (fx) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
S3C72H8/p72h8 electrical data 16- 7 1.5 mhz cpu clock 1.05 mhz 750 khz 15.625 khz main osc frequency 4.19 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1.8 v 2.7 v 5.5 v figure 16- 1. standard operating voltage range 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 16- 2. a.c timing measure pints (except for x in and xt in )
electrical data S3C72H8/p72h8 16- 8 execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operationg mode data retention mode t srel t wait reset v dd figure 16- 3. stop mode release timing when initiated by reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 16- 4. stop release timing when initiated by interrupt request x in t xh t xl 1/fx v dd - 0.5 v 0.4 v figure 16- 5. clock timing measurement at x in
S3C72H8/p72h8 electrical data 16- 9 xt in t xth t xtl 1/fxt v dd - 0.5 v 0.4 v figure 16- 6. clock timing measurement at xt in reset t rsl 0.2 v dd figure 16-7 . input timing for reset reset signal int0, 1 ks0 to ks3 t inth t intl 0.8 v dd 0.2 v dd figure 16-8 . input timing external interrupt
S3C72H8/p72h8 mechanical data 17- 1 17 mechanical data overview the S3C72H8/p72h8 microcontroller is available in a 64-pin qfp package (samsung: 64-qfp-1420f) package dimensions are shown in figure 17-1 64-qfp-1420f #64 #1 note : dimensions are in millimeters. 20.00 0.2 14.00 0.2 17.90 0.3 23.90 0.3 (1.00) (1.00) 0.80 0.20 0.05-0.25 2.65 0.10 3.00 max 0.15 +0.10 -0.05 0-8 1.00 0.15 max 0.40+0.10 -0.05 0.80 0.20 0.10 max figure 17-1. 64 -qfp-14 20f package dimensions
S3C72H8/p72h8 s3p72 h8 otp 18- 1 1 8 s3p72h8 otp overview the s3p72h8 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C72H8 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the s3p72h8 is fully compatible with the S3C72H8, both in function and in pin configuration. because of its simple programming requirements, the s3p72h8 is ideal for use as an evaluation chip for the S3C72H8.
s3p72h8 otp S3C72H8/p72h8 18- 2 ca cb v lc0 v lc1 v lc2 p0.0/extref sdat /p0.1 sclk /p0.2 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset p2.0/int0 p2.1/int1 p2.2/tcl0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 fcl/p2.3 tclo0/p3.0 btco/p3.1 clo/p3.2 buz/p3.3 ks0/p6.0 ks1/p6.1 ks2/p6.2 ks3/p6.3 c0p/p4.0 c0n/p4.1 c0out/p4.2 c1out/p4.3 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 p5.1/c1n p5.0/c1p s3p72h8 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 figure 18-1. s3p72h8 pin assignments
S3C72H8/p72h8 s3p72 h8 otp 18- 3 table 18-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.1 sdat 7 i/o serial data pin. output port when reading and input port when writing can be assigned as input/push-pull output port respectively. p0.2 sclk 8 i/o serial clock pin. input only pin. test v pp (test) 13 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 16 i chip initialization v dd / v ss v dd / v ss 9/10 i logic power supply pin. v dd should be tied to + 5 v during programming. table 18-2. comparison of s3p72h8 and S3C72H8 features characteristic s3p72h8 S3C72H8 program memory 8 k-byte eprom 8 k-byte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 64 qfp 64 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72h8, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 18-3 below. table 18-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address (a15-a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3p72h8 otp S3C72H8/p72h8 18- 4 table 18-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (note) i dd1 main operation mode: v dd = 5 v 10%, 6-mhz crystal ? 3.5 8 ma v dd = 5 v 10%, 4.19 mhz 2.5 5.5 v dd = 3 v 10%, 6-mhz crystal 1.6 4 v dd = 3 v 10%, 4.19 mhz 1.2 3 i dd2 main idle mode: v dd = 5 v 10%, 6-mhz crystal ? 1.8 3.5 v dd = 5 v 10%, 4.19 mhz 1.4 3.0 v dd = 3 v 10%, 6-mhz crystal 0.6 1.2 v dd = 3 v 10%, 4.19 mhz 0.5 1.1 i dd3 sub operation mode: v dd = 3 v , 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 15 30 ua i dd4 sub idle mode; v dd = 3 .0, 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 6 15 i dd5 stop mode; main & sub osc stop, v dd =5 v 10% except i vd, i vld, icomp and external load. scmod = 0100b xt in = 0v- ? 0.3 3 ua stop & sub osc stop, v dd = 3 v , except i vd, i vld, lcomp and external load. 0.1 1 note: supply current does not include current drawn through internal pull-up resistors or external output current loads. i lcd is lcd controller/driver operating current, i vb is voltage booster current, icomp is comparator current, and i vld is voltage level detector current.
S3C72H8/p72h8 s3p72 h8 otp 18- 5 1.5 mhz cpu clock 1.05 mhz 750 khz 15.625 khz main osc frequency 4.19 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1.8 v 2.7 v 5.5 v figure 18-2 . standard operating voltage range
s3p72h8 otp S3C72H8/p72h8 18- 6 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 18-3. otp programming algorithm

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